GS2961A Datasheet, PDF (27/104 Pages) Gennum Corporation – Ancillary data extraction

September 2012
54385 - 2
Data Sheet
27 of 104
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
The GS2961A distinguishes between Level A and Level B mappings at 3Gb/s. When
Level B data is detected, each 10-bit link is demultiplexed into its individual component
streams, and most video processing features, including error detection and correction
are enabled separately for Data Stream 1 and Data Stream 2 (Link A and Link B,
respectively). Note that ancillary data extraction can only be enabled for one link for
3Gb/s Level B data. Data Stream 1 or Data Stream 2 can be selected via the host interface.
“double” TRS headers from
interleaved HD-SDI;
Figure 4-2:Level B Mapping
Data Stream 1
(”Link A”)
EAV
Data Stream 2
(”Link 2”)
Active Video
SAV
HANC
multiplexed Y/C data
4.2.2 Level B Mapping
The 2 x 292 HD SDI interface - this can be two distinct links running at 1.5Gb/s or one
3Gb/s link formatted according to SMPTE 292 on two 10-bit links (Y/C interleaved). For
1080p/50/59.94/60 4:2:2 video formats, each link should be line-interleaved as per
SMPTE 372M. See Figure 4-2:
Figure 4-1:Level A Mapping
Data Stream 1
EAV
Data Stream 2
Active Video
SAV
HANC
NOTE: for 3Gb/s 10-bit mode the device operates in Dual Data Rate (DDR) mode, where
the data is sampled at both the rising and falling edges of the clock. This reduces the I/O
speed requirements of the downstream devices.
4.2 SMPTE 425M Mapping - 3G Level A and Level B Formats
4.2.1 Level A Mapping
Direct image format mapping - the mapping structure used to define 1080p/50/59.94/60
4:2:2 YCbCr 10 bit data, as supported by the GS2961A. See Figure 4-1: