GS2961A Datasheet, PDF (32/104 Pages) Gennum Corporation – Ancillary data extraction

4.7 Lock Detect
The LOCKED output signal is available by default on the STAT3 output pin, but may be
programmed to be output through any one of the six programmable multi-functional
pins of the device; STAT[5:0].
The LOCKED output signal is set HIGH by the Lock Detect block under the following
conditions:
Table 4-4: Lock Detect Conditions
Mode of Operation
Data-Through Mode
SMPTE Mode
SMPTE Mode with Lock
Noise-Immunity
Enabled
DVB_ASI Mode
Mode Setting
Condition for Locked
SMPTE_BYPASS = LOW
DVB_ASI = LOW
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Bit 0x085[10] set to 1
AUTO/MAN = HIGH
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
Bit AUTO/MAN = LOW
Reclocker PLL is locked.
Reclocker PLL is locked. Three
consecutive TRS words are detected in
a two-line window.
Reclocker PLL is locked. Two
consecutive TRS words are detected in
a two-line window. The last two
detected TRS words must have the
same alignment.
NOTE: Auto mode only. Not
supported in Manual mode.
Reclocker PLL is locked. 32 consecutive
DVB_ASI words with no errors are
detected within a 128-word window.
NOTE 1: The part will lock to ASI Auto mode, but could falsely unlock for some ASI
input patterns.
NOTE 2: In Standby mode, the reclocker PLL unlocks. However, the LOCKED signal
retains whatever state it previously held. So, if before Standby assertion, the LOCKED
signal is HIGH, then during standby, it remains HIGH regardless of the status of the PLL.
4.7.1 Asynchronous Lock
The lock detection algorithm is a continuous process, beginning at device power-up or
after a system reset. It continues until the device is powered down or held in reset.
The device first determines if a valid serial digital input signal has been presented to the
device. If no valid serial data stream has been detected, the serial data into the device is
considered invalid, and the LOCKED signal is LOW.
Once a valid input signal has been detected, the asynchronous lock algorithm enters a
“hunt” phase, in which the device attempts to detect the presence of either TRS words or
DVB-ASI sync words.
By default, the device powers up in auto mode (the AUTO/MAN bit in the host interface
is set HIGH). In this mode, the device operating frequency toggles between 3G, HD and
SD rates as it attempts to lock to the incoming data rate. The PCLK output continues to
operate, and the frequency may switch between 148.5MHz, 74.25MHz, 27MHz and
13.5MHz.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
32 of 104