GS2961A Datasheet, PDF (39/104 Pages) Gennum Corporation – Ancillary data extraction

Table 4-6: GS2961A PCLK Output Rates (Continued)
Output Data
Format
10-bit data output
SD format
10-bit ASI output
SD format
20bit/
10bit
LOW
LOW
Pin/Control Bit Settings
RATE_DET0 RATE_DET1
HIGH
X
SMPTE_
BYPASS
LOW
HIGH
X
LOW
DVB-ASI
LOW
HIGH
4.9.6 DDR Parallel Clock Timing
The GS2961A has the ability to transmit 10-bit parallel video data with a DDR (Dual Data
Rate) pixel clock over a single-ended interface. DDR Mode can be enabled when the SDI
data bandwidth is 3Gb/s. In this case, the 10-bit parallel data rate is 297Mb/s, and the
frequency of the DDR clock is 148.5MHz (10-bit output in 3G mode).
The DDR pixel clock avoids the need to operate a high-drive pixel clock at 297MHz. This
reduces power consumption, clock drive strength, and noise generation, and precludes
from generating excessive EMI had PCLK on the board have to run at 297MHz. It also
enables easier board routing and avoids the need to use the higher-speed I/Os on FPGAs,
which may require more expensive speed grades.
Figure 4-8 and Figure 4-9 show how the DDR interface operates. The pixel clock is
transmitted at half the data rate, and the interleaved data is sampled at the receiver on
both clock edges.
PCLK Rate
27MHz
27MHz
20-bit bus
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
(transition rate = 74.25MHz) _Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
10-bit bus
(transition rate = 148.5MHz)
Y0
Cb
0
Y1
Cr
0
Y2
Cb
1
Y3
Cr
1
Y4
Cb
2
Y5
Cr
2
Y6
Cb
3
Y7
Cr
3
Y8
Cb
4
Y9
Cr
4
PCLK
(148.5MHz)
Figure 4-8:DDR Video Interface - 3G Level A
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
39 of 104