GS2961A Datasheet, PDF (46/104 Pages) Gennum Corporation – Ancillary data extraction

Table 4-8: Output Signals Available on Programmable Multi-Function Pins (Continued)
Status Signal
Selection Code
Default Output Pin
VIDEO ERROR
0111
−
EDH DETECTED
1001
−
CARRIER DETECT
1010
−
RATE_DET0
1011
−
RATE_DET1
1100
−
NOTE:
Each of the STAT[5:0] pins are configurable individually using the register bits in the host interface; STAT[5:0]_CONFIG (008h/009h).
4.12 H:V:F Timing Signal Generation
The GS2961A extracts critical timing parameters from the received TRS words.
Horizontal blanking (H), Vertical blanking (V), and Field odd/even (F) timing are output
on the STAT[2:0] pins by default.
Using the H_CONFIG bit in the host interface, the H signal timing can be selected as one
of the following:
1. Active line blanking (H_CONFIG = LOW) - the H output is HIGH for the horizontal
blanking period, including the EAV TRS words.
2. TRS based blanking (H_CONFIG = HIGH) - the H output is set HIGH for the entire
horizontal blanking period as indicated by the H bit in the received TRS signals.
The timing of these signals is shown in Figure 4-15 below.
NOTE: Both 8-bit and 10-bit TRS words are identified by the device.
PCLK
LUMA DATA
CHROMA DATA
H
V
F
3FF
000
000 XYZ (EAV)
3FF
000
000 XYZ (EAV)
3FF
000
000 XYZ (SAV)
3FF
000
000 XYZ (SAV)
Figure 4-12:H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode
PCLK (3G DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (3G)
H
V
F
3FF
3FF
000
000
000
000 XYZ (EAV) XYZ (EAV)
H VF T IM IN G A T E A V
PCLK (3G DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (3G)
H
V
F
3FF
3FF
000
000
000
000 XYZ (SAV) XYZ (SAV)
H VF T IM IN G A T S A V
H S IG N A L T IM IN G :
H _C O N F IG = LO W
H _C O N F IG = H IG H
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
46 of 104