GS2961A Datasheet, PDF (56/104 Pages) Gennum Corporation – Ancillary data extraction

VIDEO_FORMAT_352_A_X and VIDEO_FORMAT_352_B_X registers, and are updated
once per frame at the end of line 12.
The raster structure registers also contain three status bits: STD_LOCK, INT/PROG and
M. The STD_LOCK bit is set HIGH whenever the timing signal generator is fully
synchronized to the incoming standard, and detects it as one of the supported formats.
The INT/PROG bit is set HIGH if the detected video standard is interlaced and LOW if the
detected video standard is progressive. M is set HIGH if the clock frequency includes the
“1000/1001” factor denoting a 23.98, 29.97 or 59.94Hz frame rate.
The video standard code is reported in the VD_STD bits of the host interface register.
Table 4-11 describes the 5-bit codes for the recognized video standards.
Table 4-11: Supported Video Standard Codes
SMPTE Active Video Area
Standard
RATE_
DET[1]
HD/3G
RATE_
DET[0]
SD/HD
425M (3G 1920x1080/60 (1:1)
1
0
Level A)
4:2:2
1920x1080/50 (1:1)
1
0
425M (3G 1920x1080/60 (2:1)
1
0
Level B
DS1 and
1920x1080/50 (2:1)
1
0
DS2) 4:2:2
425M (3G) 1920x1080/60 (2:1) or
1
0
4:4:4
1920x1080/30 (PsF)
1920x1080/50 (2:1) or
1
0
1920x1080/25 (PsF)
1280x720/60 (1:1)
1
0
1280x720/50 (1:1)
1
0
1920x1080/30 (1:1)
1
0
1920x1080/25 (1:1)
1
0
1280x720/25 (1:1)
1
0
1920x1080/24 (1:1)
1
0
1280x720/24 (1:1)
1
0
260M (HD) 1920x1035/60 (2:1)
0
0
295M (HD) 1920x1080/50 (2:1)
0
0
Lines
per
Frame
1125
1125
1125
1125
Active
Lines per
Frame
1080
1080
540
540
Words
per
Active
Line
1920
1920
1920
1920
Words VD_STD
per Line
[5:0]
2200
2Bh
2640
2Dh
2200
0Ah
2640
0Ch
1125
1080
3840
4400
2Ah
1125
1080
3840
5280
2Ch
750
720
2560
3300
20h
750
720
2560
3960
24h
1125
1080
3840
4400
2Bh
1125
1080
3840
5280
2Dh
750
720
2560
7920
26h
1125
1080
3840
5500
30h
750
720
2560
8250
28h
1125
1035
1920
2200
15h
1250
1080
1920
2376
14h
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
56 of 104