GS2961A Datasheet, PDF (30/104 Pages) Gennum Corporation – Ancillary data extraction

4.5.1 PLL Loop Bandwidth
The fine frequency and phase lock loop in the GS2961A reclocker is non-linear. The PLL
loop bandwidth scales with the jitter amplitude of the input data stream; automatically
reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the
jitter in the input data stream and produce a very clean reclocked output.
The loop bandwidth of the GS2961A PLL is defined with 0.2UI input jitter. The
bandwidth is controlled by the LB_CONT pin. Under nominal conditions, with the
LB_CONT pin floating and 0.2UI input jitter applied, the loop bandwidth is set to 1/1000
of the frequency of the input data stream. Connecting the LB_CONT pin to 3.3V reduces
the bandwidth to half of the nominal setting. Connecting the LB_CONT pin to GND
increases the bandwidth to double the nominal setting. Table 4-2 below summarizes this
information.
Table 4-2: PLL Loop Bandwidth
Input Data Rate
LB_CONT Pin Connection
SD
3.3V
Floating
0V
HD
3.3V
Floating
0V
3G
3.3V
Floating
0V
1_{Measured with 0.2UI input jitter applied}
Loop Bandwidth (MHz)¹
0.135
0.27
0.54
0.75
1.5
3.0
1.5
3.0
6.0
4.6 External Crystal/Reference Clock
The GS2961A requires an external 27MHz reference clock for correct operation. This
reference clock is generated by connecting a crystal to the XTAL1 and XTAL2 pins of the
device. See Application Reference Design on page 98. Table 4-3 shows XTAL
characteristics.
Alternately, a 27MHz external clock source can be connected to the XTAL1 pin of the
device, as shown in Figure 4-4.
The frequency variation of the crystal including aging, supply and temperature
variation, should be less than +/-100ppm.
The equivalent series resistance (or motional resistance) should be a maximum of 50Ω.
The external crystal is used in the frequency acquisition process. It has no impact on the
output jitter performance of the part when the part is locked to incoming data. Because
of this, the only key parameter is the frequency variation of the crystal that is stated
above.
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
30 of 104