GS2961A Datasheet, PDF (36/104 Pages) Gennum Corporation – Ancillary data extraction

I/O Timing Specs:
DDR Mode:
DBUS[19:10]
6.734ns
3.367ns
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
PCLK_OUT
toh
tod
toh
tod
80%
20%
tr
80%
20%
tf
dbus
stat
toh
0.450ns
0.450ns
tr/tf (min)
0.400ns
0.500ns
3.3V
Cload
tod tr/tf (max)
6 pF
1.900ns 1.500ns
2.200ns 1.600ns
10b3G Mode
Cload
15 pF
toh
0.400ns
0.450ns
tr/tf (min)
0.300ns
0.400ns
1.8V
Cload
tod
6 pF
1.800ns
2.500ns
tr/tf (max)
1.100ns
1.500ns
Cload
15 pF
Figure 4-7:PCLK to Data and Control Signal Output Timing - DDR Mode
The GS2961A has a 20-bit output parallel bus, which can be configured for different
output formats as shown in Table 4-5.
Table 4-5: GS2961A Output Video Data Format Selections
Output Data
Format
20-bit
demultiplexed HD
format
20-bit data output
HD format
20-bit
demultiplexed SD
format
20-bit data output
SD format
10-bit multiplexed
3G DDR format
10-bit multiplexed
HD format
10-bit data output
HD format
20BIT
/10BIT
HIGH
Pin/Register Bit Settings
RATE_
SEL0
LOW
RATE_
SEL1
LOW
SMPTE_
BYPASS
HIGH
HIGH
HIGH
LOW
HIGH
LOW
X
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
X
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
DVB-ASI
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DOUT[9:0]
Chroma
DATA
Chroma
DATA
Driven LOW
Driven LOW
Driven LOW
DOUT[19:10]
Luma
DATA
Luma
DATA
Data Stream One/
Data Stream Two*
Luma/Chroma
DATA
GS2961A 3Gb/s, HD, SD SDI Integrated Receiver
Data Sheet
54385 - 2
September 2012
36 of 104