K5D5657ACM Datasheet, PDF (57/74 Pages) Samsung semiconductor – 256Mb NAND and 256Mb Mobile SDRAM

K5D5657ACM-F015
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MCP MEMORY
Power Up Sequence for Mobile SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CLOCK
CKE
Hi
CS
RAS
CAS
ADDR
Key
Key
RAa
BA0
BA1
A10/AP
RAa
DQ
Hi-Z
Hi-Z
WE
DQM
High level is necessary
tRP
Precharge
(All Bank)
Auto
Refresh
tARFC
Auto
Refresh
tARFC
Normal
MRS
Extended
MRS
Row Active
(A-Bank)
*NOTE:
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
: Don’t care
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is half driver strength, all 4 banks refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again
at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
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Revision 0.1
September 2003