K5D5657ACM Datasheet, PDF (52/74 Pages) Samsung semiconductor – 256Mb NAND and 256Mb Mobile SDRAM

K5D5657ACM-F015
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MCP MEMORY
12. About Burst Type Control
Basic
MODE
Sequential Counting
Interleave Counting
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting.
Random
MODE
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
Basic
MODE
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010".
8
At MRS A2,1,0 = "011".
Full Page
At MRS A2,1,0 = "111".
Wrap around mode(infinite burst length) should be stopped by burst stop.
RAS interrupt or CAS interrupt.
Special
MODE
BRSW
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1.
At auto precharge of write, tRAS should not be violated.
Random
MODE
Burst Stop
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Interrupt
MODE
RAS Interrupt
(Interrupted by Precharge)
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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Revision 0.1
September 2003