K5D5657ACM Datasheet, PDF (44/74 Pages) Samsung semiconductor – 256Mb NAND and 256Mb Mobile SDRAM

K5D5657ACM-F015
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MCP MEMORY
D. DEVICE OPERATIONS (continued)
BURST WRITE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be com-
pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using Pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after all banks have satisfied tRAS(min) require-
ment, performs precharge on all banks. At the end of tRP after
performing precharge to all the banks, all banks are in idle state.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1
of the bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto pre-
charge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
AUTO REFRESH
The storage cells of 64Mb, 128Mb, 256Mb and 512Mb SDRAM
need to be refreshed every 64ms to maintain data. An auto
refresh cycle accomplishes refresh of a single row of storage
cells. The internal counter increments automatically on every
auto refresh cycle to refresh all the rows. An auto refresh com-
mand is issued by asserting low on CS, RAS and CAS with high
on CKE and WE. The auto refresh command can only be
asserted with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified by
tRC(min). The minimum number of clock cycles required can be
calculated by driving tRC with clock cycle time and them rounding
up to the next higher integer. The auto refresh command must be
followed by NOP's until the auto refresh operation is completed.
All banks will be in the idle state at the end of auto refresh opera-
tion. The auto refresh is the preferred refresh mode when the
SDRAM is being used for normal data transactions. The 64Mb
and 128Mb SDRAM’s auto refresh cycle can be performed once
in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.
The 256Mb and 512Mb SDRAM’s auto refresh cycle can be per-
formed once in 7.8us or a burst of 8192 auto refresh cycles once
in 64ms.
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Revision 0.1
September 2003