4513_03 Datasheet, PDF (99/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
CONTROL REGISTERS
Serial I/O mode register J1
J13
Not used
Serial I/O internal clock dividing ratio
J12
selection bit
J11
Serial I/O port selection bit
J10 Serial I/O synchronous clock selection bit
A-D control register Q1
at reset : 00002
at RAM back-up : state retained
R/W
0
This bit has no function, but read/write is enabled.
1
0
Instruction clock signal divided by 8
1
Instruction clock signal divided by 4
0
Input ports P20, P21, P22 selected
1
Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected
0
External clock
1
Internal clock (instruction clock divided by 4 or 8)
at reset : 00002
at RAM back-up : state retained
R/W
Q13 Note used
0
This bit has no function, but read/write is enabled.
1
Q12Q11Q10
Selected pins
Q12
0 0 0 AIN0
0 0 1 AIN1
0 1 0 AIN2
Q11 Analog input pin selection bits (Note 2) 0 1 1 AIN3
1 0 0 AIN4 (Not available for the 4513 Group)
1 0 1 AIN5 (Not available for the 4513 Group)
Q10
1 1 0 AIN6 (Not available for the 4513 Group)
1 1 1 AIN7 (Not available for the 4513 Group)
A-D control register Q2
at reset : 00002
at RAM back-up : state retained
R/W
0
Q23 A-D operation mode selection bit
1
Q22
P43/AIN7 and P42/AIN6 pin function selec-
0
tion bit (Not used for the 4513 Group)
1
Q21
P41/AIN5 pin function selection bit
0
(Not used for the 4513 Group)
1
Q20
P40/AIN4 pin function selection bit
0
(Not used for the 4513 Group)
1
A-D conversion mode
Comparator mode
P43, P42
(read/write enabled for the 4513 Group)
AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group)
P41
(read/write enabled for the 4513 Group)
AIN5/P41
(read/write enabled for the 4513 Group)
P40
(read/write enabled for the 4513 Group)
AIN4/P40
(read/write enabled for the 4513 Group)
Comparator control register Q3 (Note 3)
at reset : 00002
at RAM back-up : state retained
R/W
Q33 Voltage comparator (CMP1) control bit
Q32 Voltage comparator (CMP0) control bit
Q31 CMP1 comparison result store bit
Q30 CMP0 comparison reslut store bit
0
Voltage comparator (CMP1) invalid
1
Voltage comparator (CMP1) valid
0
Voltage comparator (CMP0) invalid
1
Voltage comparator (CMP0) valid
0
CMP1- > CMP1+
1
CMP1- < CMP1+
0
CMP0- > CMP0+
1
CMP0- < CMP0+
Clock control register MR
at reset : 10002
at RAM back-up : 10002
R/W
0
MR3 System clock selection bit
1
0
MR2 Not used
1
0
MR1 Not used
1
0
MR0 Not used
1
Notes 1: “R” represents read enabled, “W” represents write enabled.
2: Select AIN4–AIN7 with register Q1 after setting register Q2.
3: Bits 0 and 1 of register Q3 can be only read.
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
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4513/4514 Group User’s Manual