4513_03 Datasheet, PDF (136/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timers
ΠDisable Interrupts
Timer 1 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
b0
Interrupt control register V1
!
0
!
!
Timer 1 interrupt occurrence
(TV1A instruction)
disabled
 Stop Timer Operation
Timer 1 and prescaler are temporarily stopped.
Dividing ratio of prescaler is selected.
Timer control register W1
b3
0
b0 _{Timer 1 stop (TW1A instruction)}
0 0 ! _{Prescaler stop}
Prescaler divided by 4 selected
Ž Set Timer Value, Select CNTR0 Output
CNTR0 output is selected.
Timer 1 count time is set.
b3
b0
Timer control register W6 ! ! 0 1 CNTR0 output selected (TW6A instruction)
Timer 1 reload register R1 “2916” Timer count value 41 set (T1AB instruction)
 Clear Interrupt Request
Timer 1 interrupt activated condition is cleared.
Timer 1 interrupt request flag T1F “0”_{g0 h}
Timer 1 interrupt activated condition cleared
(SNZT1 instruction)
Note when the interrupt request is cleared
When  is executed, considering the skip of the next instruction according to the
interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
 Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3
b0
Timer control register W1 1 0 1 ^{! Timer 1 operation start (TW1A instruction)}
Prescaler operation start
‘ Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
! 1!!
Timer 1 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
’ Stop CNTR0 Output
D6/CNTR0 pin is set to CNTR0 input pin, and it is set to the high-impedance state.
b3
b0
Timer control register W6 ! ! 0 0 CNTR0 input pin set (TW6A instruction)
Output latch of port D6 is set to “1.”
(SD instruction)
“!”: it can be “0” or “1.”
Fig. 2.3.4 CNTR0 output setting example
4513/4514 Group User’s Manual
2-33