4513_03 Datasheet, PDF (97/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
External 1 interrupt enable bit
V10
External 0 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
R/W
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
Interrupt disabled (SNZ1 instruction is valid)
1
Interrupt enabled (SNZ1 instruction is invalid)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V2
V23 Serial I/O interrupt enable bit
V22 A-D interrupt enable bit
V21 Timer 4 interrupt enable bit
V20 Timer 3 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
R/W
0
Interrupt disabled (SNZSI instruction is valid)
1
Interrupt enabled (SNZSI instruction is invalid)
0
Interrupt disabled (SNZAD instruction is valid)
1
Interrupt enabled (SNZAD instruction is invalid)
0
Interrupt disabled (SNZT4 instruction is valid)
1
Interrupt enabled (SNZT4 instruction is invalid)
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
Interrupt control register I1
I13
Not used
Interrupt valid waveform for INT0 pin/
I12
return level selection bit (Note 2)
I11
INT0 pin edge detection circuit control bit
INT0 pin
I10
timer 1 control enable bit
at reset : 00002
at RAM back-up : state retained
R/W
0
1
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
1
instruction)/“H” level
0
One-sided edge detected
1
Both edges detected
0
Disabled
1
Enabled
Interrupt control register I2
at reset : 00002
at RAM back-up : state retained
R/W
I23
Not used
Interrupt valid waveform for INT1 pin/
I22
return level selection bit (Note 3)
0
This bit has no function, but read/write is enabled.
1
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
0
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
1
instruction)/“H” level
I21
INT1 pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT1 pin
I20
timer 3 control enable bit
0
Disabled
1
Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
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4513/4514 Group User’s Manual