4513_03 Datasheet, PDF (67/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTION BLOCK OPERATIONS
(4) Return signal
An external wakeup signal is used to return from the RAM back-up
mode because the oscillation is stopped. Table 21 shows the return
condition for each return source.
(5) Ports P0 and P1 control registers
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup func-
tion. Set the contents of this register through register A with the
TK0A instruction. In addition, the TAK0 instruction can be used to
transfer the contents of register K0 to register A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up
transistor. Set the contents of this register through register A with
the TPU0A instruction. In addition, the TAPU0 instruction can be
used to transfer the contents of register PU0 to register A.
Table 21 Return source and return condition
Return source
Return condition
Ports P0, P1
Return by an external falling
edge input (“H”→“L”).
Port P30/INT0
Port P31/INT1
Return by an external “H” level or
“L” level input.
The EXF0 flag is not set.
Return by an external “H” level or
“L” level input.
The EXF1 flag is not set.
Remarks
Set the port using the key-on wakeup function selected with register K0 to
“H” level before going into the RAM back-up state because the port P0
shares the falling edge detection circuit with port P1.
Select the return level (“L” level or “H” level) with the bit 2 of register I1 ac-
cording to the external state before going into the RAM back-up state.
Select the return level (“L” level or “H” level) with the bit 2 of register I2 ac-
cording to the external state before going into the RAM back-up state.
1-54
4513/4514 Group User’s Manual