4513_03 Datasheet, PDF (150/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.4 Serial I/O
ΠDisable Interrupts
Serial I/O interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Interrupt control register V2
b3
0
!
b0
!!
Serial I/O interrupt
(TV2A instruction)
occurrence
disabled
 Set Serial I/O
b3
b0
Serial I/O mode register J1 ! _! 1 0
Exernal clock selected (TJ1A instruction)
Serial I/O port selected
Ž Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive
completion flag SIOF
“0”_g0
h
Serial I/O interrupt activated condition cleared
(SNZSI instruction)
Note when the interrupt request is cleared
When Ž is executed, considering the skip of the next instruction according to the
SIOF flag, insert the NOP instruction after the SNZSI instruction.
When interrupt is
not used
 Set Interrupt
Interrupts except serial I/O is enabled
(EI instruction)
When interrupt is used
 Set Interrupt
Serial I/O interrupt temporarily disabled is enabled.
Interrupt control register V2
b3
1
b0
!!!
Serial I/O interrupt occurrence
enabled (TV2A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled
(EI instruction)
 Set When Transmit/Receive Operation Start Enabled
Serial transfer start state (SST instruction)
System enters to control signal transmission enabled state (“L” level)
However, SCK pin initial level = “H” level
‘ Start Serial I/O Operation
Serial transfer starts by clock of master side
’ Check Serial I/O Interrupt Request
SIOF flag is checked (SNZSI instruction).
’ Serial I/O Interrupt Occur
“ Receive Data Processing
System enters to control signal transmission disabled state (“H” level)
Data processing received by serial transfer is executed.
Register SI → register A, register B (TABSI instruction)
When serial communication is executed,  to “ are repeated.
“!”: it can be “0” or “1.”
Fig. 2.4.6 Slave serial I/O example
4513/4514 Group User’s Manual
2-47