4513_03 Datasheet, PDF (44/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTION BLOCK OPERATIONS
Instruction clock
W13
Prescaler
W12
Divistion circuit _MR3
(divided by 2)
1 ^{Internal clock}
generating circuit
XIN
0 _{(divided by 3)}
0
1/4
0
1
1/16
1
P30/INT0
I12
Falling One-sided edge
0 ^{detection circuit}
1 _{Both edges}
Rising detection circuit
W11 (Note 3)
0
1
ORCLK
I11
0 _{(Note 1)}
SQ
W10
1
1
0
I10 R
Timer 1 (8)
(TAB1)
Reload register R1 (8)
T1AB _(TR1AB) T1AB
Register B Register A
T1F ^{Timer 1}
interrupt
P31/INT1
W21,W20
Timer 1 underflow signal
00
W23(Note 3)
01
0
1
10 ^{Not available}
Timer 2 (8)
11
Reload register R2 (8)
(TAB2)
(T2AB)
Register B Register A
I22
Falling One-sided edge
0 ^{detection circuit}
1 Both edges
Rising detection circuit
W31,W30
00
W33(Note 3)
01
0
1
10Not available
11Not available
(TAB3)
I21
Timer 2 underflow signal
0 _{(Note 2)}
W32
SQ
1
1
0
I20 R
Timer 3 (8)
Reload register R3 (8)
T3AB _(TR3AB) T3AB
Register B Register A
T2F ^{Timer 2}
interrupt
T3F Timer 3
interrupt
W41,W40
Timer 3 underflow signal
00
W43(Note 3)
01
0
10Not available
1
Timer 4 (8)
11Not available
Reload register R4 (8)
(TAB4)
(T4AB)
Register B Register A
T4F
Timer 4
interrupt
Data is set automatically from each reload
register when timer 1, 2, 3, or 4 underflows
(auto-reload function)
Instruction clock ^{16-bit timer (WDT)}
1 - - - - - - - - - - - 15 16
Notes 1: Timer 1 count start synchronous circuit is set
by the valid edge of P30/INT0 pin selected by
bits 1 (I11) and 2 (I12) of register I1.
WRST instruction
2: Timer 3 count start synchronous circuit is set
Reset signal
S
WEF Q
R
by the valid edge of P31/INT1 pin selected by
bits 1 (I21) and 2 (I22) of register I2.
3: Count source is stopped by clearing to “0.”
Fig. 19 Timers structure
WDF1 WDF2
System reset
4513/4514 Group User’s Manual
1-31