4513_03 Datasheet, PDF (24/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
PIN DESCRIPTION
PORT FUNCTION
Port
Pin
Port D
Port P0
D0–D5
D6/CNTR0
D7/CNTR1
P00–P03
Input
Output
I/O
(8)
Output structure
N-channel open-drain
I/O N-channel open-drain
(4)
Port P1 P10–P13
I/O N-channel open-drain
(4)
Port P2
Port P3
(Note 1)
Port P4
(Note 2)
Port P5
(Note 2)
P20/SCK
P21/SOUT
P22/SIN
P30/INT0
P31/INT1
P32, P33
P40/AIN4
–P43/AIN7
P50–P53
Input
(3)
I/O N-channel open-drain
(4)
I/O N-channel open-drain
(4)
I/O CMOS
(4)
Notes 1: The 4513 Group does not have P32 and P33.
2: The 4513 Group does not have these ports.
I/O
Control
Control
unit instructions registers
Remark
1
SD, RD
SZD
W6
CLD
4
OP0A
IAP0
PU0, K0
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
4
OP1A
IAP1
PU0, K0
Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)
3
IAP2
J1
4
OP3A
IAP3
4
OP4A
IAP4
4
OP5A
IAP5
I1, I2
Q2
FR0
Built-in key-on wakeup
function
(P30/INT0, P31/INT1)
DEFINITION OF CLOCK AND CYCLE
q System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bit 3 of the clock control reg-
ister MR.
Table Selection of system clock
Register MR
MR3
0
1
System clock
f(XIN)
f(XIN )/2
Note: f(XIN)/2 is selected after system is released from reset.
q Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
4513/4514 Group User’s Manual
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