4513_03 Datasheet, PDF (149/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.4 Serial I/O
ΠDisable Interrupts
Serial I/O interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
Interrupt control register V2
b3
0
!
b0
!!
Serial I/O interrupt
(TV2A instruction)
occurrence
disabled
 Set Serial I/O
b3
b0 _{Internal clock selected (TJ1A instruction)}
Serial I/O mode register J1 ! 1 1 1 _{Serial I/O port selected}
Dividing ratio = 4 selected
Ž Clear Interrupt Request
Serial I/O interrupt activated condition is cleared.
Serial I/O transmit/receive “0”_{g0 h}
completion flag SIOF
Serial I/O interrupt activated condition cleared
(SNZSI instruction)
Note when the interrupt request is cleared
When Ž is executed, considering the skip of the next instruction according to the
SIOF flag, insert the NOP instruction after the SNZSI instruction.
When interrupt is
not used
 Set Interrupt
Interrupts except serial I/O is enabled
(EI instruction)
When interrupt is used
 Set Interrupt
Serial I/O interrupt temporarily disabled is enabled.
Interrupt control register V2
b3
1
b0
!!!
Serial I/O interrupt occurrence
enabled (TV2A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled
(EI instruction)
 Start Condition of Serial I/O operation
Slave side is enabled to receive is checked.
Pin level of control signal = “L”
‘ Start Serial I/O Operation
Serial transfer is started (SST instruction) after checking
slave side is enabled to receive.
g0 h
’ Check Serial I/O Interrupt Request
SIOF flag is checked (SNZSI instruction).
’ Serial I/O Interrupt Occur
“ Execute Receive Data
Data received by serial transfer is executed.
Register SI → register A, register B (TABSI instruction)
When serial communication is executed,  to “ are repeated.
“!”: it can be “0” or “1.”
Fig. 2.4.5 Master serial I/O setting example
2-46
4513/4514 Group User’s Manual