4513_03 Datasheet, PDF (70/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTION BLOCK OPERATIONS
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to switch the middle-speed mode and high-speed
mode
• Control circuit to return from the RAM back-up state
XIN
XOUT
Oscillation
circuit
Division circuit
(divided by 2)
MR3
1
0
Internal clock
generation circuit
(divided by 3)
System clock
Instruction clock
Counter
POF instruction
R
Q
S
Wait time (Note) _Software
control circuit
start signal
RESET
Key-on wake up control register
K00,K01,K02,K03
Falling detected
Multi-
plexer
Ports P00, P01
Ports P02, P03
Ports P10, P11
Ports P12, P13
I12
“L” level
0
P30/INT0
1
“H” level
I22
“L” level
0
1
“H” level
P31/INT1
Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.
Fig. 41 Clock control circuit structure
Table 23 Clock control register MR
Clock control register MR
at reset : 10002
at RAM back-up : 10002
0
MR3 System clock selection bit
1
0
MR2 Not used
1
0
MR1 Not used
1
0
MR0 Not used
1
Note : “R” represents read enabled, and “W” represents write enabled.
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
4513/4514 Group User’s Manual
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