4513_03 Datasheet, PDF (121/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
ΠDisable Interrupts
INT0 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3 b0 _{INT0 interrupt occurrence disabled}
Interrupt control register V1 ! ! ! 0 _{(TV1A instruction)}
 Set Port
Port used for INT0 interrupt is set to input port.
b3
b0
Port P30 output latch ^{! ! ! 1} Set to input (OP3A instruction)
Ž Set Valid Waveform
Valid waveform of INT pin is selected.
Both edges detection selected
b3
b0
Interrupt control register I1 ! ! 1 ! Both edges detection selected (TI1A instruction)
 Clear Interrupt Request
External interrupt activated condition is cleared.
INT0 interrupt request flag EXF0 “0”
INT0 interrupt activated condition cleared
(SNZ0 instruction)
Note when the interrupt request is cleared
When  is executed, considering the skip of the next instruction according to the
interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
 Enable Interrupts
The INT0 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
!
!!
b0
1
INT0 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
“!”: it can be “0” or “1.”
INT0 interrupt execution started
Fig. 2.2.2 INT0 interrupt setting example
Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more
of system clock.
2-18
4513/4514 Group User’s Manual