4513_03 Datasheet, PDF (45/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTION BLOCK OPERATIONS
Table 10 Timer control registers
Timer control register W1
at reset : 00002
at RAM back-up : 00002
R/W
W13 Prescaler control bit
W12 Prescaler dividing ratio selection bit
W11 Timer 1 control bit
W10 ^{Timer 1 count start synchronous circuit}
control bit
0
Stop (state initialized)
1
Operating
0
Instruction clock divided by 4
1
Instruction clock divided by 16
0
Stop (state retained)
1
Operating
0
Count start synchronous circuit not selected
1
Count start synchronous circuit selected
Timer control register W2
W23 Timer 2 control bit
W22 Not used
W21
Timer 2 count source selection bits
W20
at reset : 00002
at RAM back-up : state retained
R/W
0 Stop (state retained)
1 Operating
0
This bit has no function, but read/write is enabled.
1
W21 W20
Count source
0 0 Timer 1 underflow signal
0 1 Prescaler output
1 0 CNTR0 input
1 1 16 bit timer (WDT) underflow signal
Timer control register W3
at reset : 00002
at RAM back-up : state retained
R/W
W33 Timer 3 control bit
0 Stop (state retained)
1 Operating
W32 ^{Timer 3 count start synchronous circuit}
control bit
0 Count start synchronous circuit not selected
1 Count start synchronous circuit selected
W31 W30
Count source
W31
0 0 Timer 2 underflow signal
Timer 3 count source selection bits
0 1 Prescaler output
W30
1 0 Not available
1 1 Not available
Timer control register W4
W43 Timer 4 control bit
W42 Not used
W41
Timer 4 count source selection bits
W40
at reset : 00002
at RAM back-up : state retained
R/W
0 Stop (state retained)
1 Operating
0
This bit has no function, but read/write is enabled.
1
W41 W40
Count source
0 0 Timer 3 underflow signal
0 1 Prescaler output
1 0 CNTR1 input
1 1 Not available
Timer control register W6
at reset : 00002
at RAM back-up : state retained
R/W
0
W63 CNTR1 output control bit
1
0
W62 D7/CNTR1 function selection bit
1
0
W61 CNTR0 output control bit
1
0
W60 D6/CNTR0 output control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
Timer 3 underflow signal output divided by 2
CNTR1 output control by timer 4 underflow signal divided by 2
D7(I/O)/CNTR1 input
CNTR1 (I/O)/D7(input)
Timer 1 underflow signal output divided by 2
CNTR0 output control by timer 2 underflow signal divided by 2
D6(I/O)/CNTR0 input
CNTR0 (I/O)/D6(input)
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4513/4514 Group User’s Manual