4513_03 Datasheet, PDF (137/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timers
ΠDisable Interrupts
Timer 2 interrupt is temporarily disabled.
Interrupt enable flag INTE “0”
All interrupts disabled (DI instruction)
b3
b0
Interrupt control register V1
0
!
!
!
Timer 2 interrupt occurrence
(TV1A instruction)
disabled
 Stop Timer Operation
Timer 1 operation is temporarily stopped.
Timer 2 count source is selected.
Timer control register W2
b3
0!
1
b0
0
Timer 2 stop (TW2A instruction)
CNTR0 input selected for count source
Ž Set Timer Value
Timer 2 count time is set.
Timer 2 reload register R2 ^{“6316”}
Timer count value 99 set (T2AB instruction)
 Clear Interrupt Request
Timer 2 interrupt activated condition is cleared.
Timer 2 interrupt request flag T2F “0”_{g0 h}
Timer 2 interrupt activated condition cleared
(SNZT2 instruction)
Note when the interrupt request is cleared
When  is executed, considering the skip of the next instruction according to the
interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
 Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3
b0
Timer control register W2 1 ! 1 0
Timer 2 operation start (TW2A instruction)
‘ Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled.
Interrupt control register V1
b3
b0
1 _{!! !}
Timer 2 interrupt occurrence enabled
(TV1A instruction)
Interrupt enable flag INTE “1”
All interrupts enabled (EI instruction)
“!”: it can be “0” or “1.”
Fig. 2.3.5 CNTR1 input setting example
However, specify the pulse width input to CNTR0 pin/CNTR1 pin. Refer to section “2.3.4 Notes on use” for
the timer external input period condition.
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4513/4514 Group User’s Manual