4513_03 Datasheet, PDF (118/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
(5) Interrupt control register I1
The INT0 pin timer 1 control enable bit is assigned to bit 0, INT0 pin edge detection circuit control
bit is assigned to bit 1, and interrupt valid waveform for INT0 pin/return level selection bit is assigned
to bit 2.
Set the contents of this register through register A with the TI1A instruction.
In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Table 2.2.3 shows the interrupt control register I1.
Table 2.2.3 Interrupt control register I1
Interrupt control register I1
at reset : 00002 at RAM back-up : state retained R/W
I13 Not used
0
This bit has no function, but read/write is enabled.
1
Falling waveform (“L” level of INT0 pin is recognized
Interrupt valid waveform for INT0 0
with the SNZI0 instruction)/“L” level
I12 pin/return level selection bit
Rising waveform (“H” level of INT0 pin is recognized
(Note 2)
1 _{with the SNZI0 instruction)/“H” level}
INT0 pin edge detection circuit 0 One-sided edge detected
I11
control bit
1 Both edges detected
INT0 pin
I10
timer 1 control enable bit
0 Disabled
1 Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set.
Accordingly, clear EXF0 flag with the SNZ0 instruction.
(6) Interrupt control register I2
The INT1 pin timer 3 control enable bit is assigned to bit 0, the INT1 pin edge detection circuit control
bit is assigned to bit 1 and the interrupt valid waveform for INT1 pin/return level selection bit is
assigned to bit 2.
Set the contents of this register through register A with the TI2A instruction.
In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A.
Table 2.2.4 shows the interrupt control register I2.
Table 2.2.4 Interrupt control register I2
Interrupt control register I2
at reset : 00002 at RAM back-up : state retained R/W
I23 Not used
0
This bit has no function, but read/write is enabled.
1
Falling waveform (“L” level of INT1 pin is recognized
Interrupt valid waveform for INT1 0
with the SNZI1 instruction)/“L” level
I22 pin/return level selection bit
Rising waveform (“H” level of INT1 pin is recognized
(Note 2)
1
with the SNZI1 instruction)/“H” level
INT1 pin edge detection circuit
I21
0
One-sided edge detected
control bit
1 Both edges detected
INT1 pin
I20
timer 3 control enable bit
0 Disabled
1 Enabled
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set.
Accordingly, clear EXF1 flag with the SNZ1 instruction.
4513/4514 Group User’s Manual
2-15