4513_03 Datasheet, PDF (56/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTION BLOCK OPERATIONS
(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
ΠWhen A-D conversion starts, the register AD is cleared to
“00016.”
 Next, the topmost bit of the register AD is set to “1,” and the
comparison voltage Vref is compared with the analog input volt-
age VIN.
Ž When the comparison result is Vref < VIN, the topmost bit of the
register AD remains set to “1.” When the comparison result is
Vref > VIN, it is cleared to “0.”
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5 µs when f(XIN) =
4.0 MHz in high-speed mode) from the start, and the conversion re-
sult is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to “1” as soon as A-D conversion
completes (Figure 27).
Table 16 Change of successive comparison register AD during A-D conversion
At starting conversion
1st comparison
2nd comparison
3rd comparison
Change of successive comparison register AD
-------------
1
0
0 ----- 0
0
0
-------------
-------------
U1
1
0 ----- 0
0
0
-------------
-------------
U1 U2
1 ----- 0
0
0
-------------
After 10th comparison
completes
A-D conversion result
-------------
U1 U2 U3 ----- U8 U9 UA
-------------
U1: 1st comparison result
U3: 3rd comparison result
U9: 9th comparison result
U2: 2nd comparison result
U8: 8th comparison result
UA: 10th comparison result
VDD
2
VDD
2
VDD
2
VDD
2
Comparison voltage (Vref) value
VDD
±
4
VDD
VDD
± ₄ ±₈
±
○
○
○
○
±
VDD
1024
4513/4514 Group User’s Manual
1-43