4513_03 Datasheet, PDF (28/210 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
PIN DESCRIPTION
PORT BLOCK DIAGRAMS (continued)
Direction register FR0i
Ai D Q
OP5A instruction T
Register A
IAP5 instruction
Register Y
SD instruction
RD instruction
Decoder ^{Skip decision}
(SZD instruction)
CLD instruction
S
RQ
P50–P53
D0–D5
Skip decision (SZD instruction)
Clock input for timer 2 event count
Register Y Decoder
SD instruction
RD instruction
CLD instruction
S
RQ
W60
0
Timer 1 underflow signal divided by 2 or
1
signal of AND operation between
timer 1 underflow signal divided by 2 and
timer 2 underflow signal divided by 2
D6/CNTR0
Skip decision (SZD instruction)
Clock input for timer 4 event count
Register Y Decoder
SD instruction
RD instruction
CLD instruction
S
RQ
W62
0
D7/CNTR1
Timer 3 underflow signal divided by 2 or
1
signal of AND operation between
timer 3 underflow signal divided by 2 and
timer 4 underflow signal divided by 2
•
This symbol represents a parasitic diode on the port.
• Applied potential to ports D0–D7 must be 12 V.
• i represents 0, 1, 2, or 3.
• The 4513 Group does not have port P5.
4513/4514 Group User’s Manual
1-15