HN29V1G91T-30 Datasheet, PDF (88/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
10. Measures for don’t care in timing waveforms for Program Data Input in Erase Busy
The timing waveforms in any mode is specified “Don’t care”, during CE = H other control signals become
“Don’t care”. When CE = H, specify ALE and CLE = H, WE and RE = H.
11. Status read during read mode (data output)
Input the status mode reset command (7Fh), when the device returns to the read mode, after the status read
is executed the status read command (70h), during the busy status in the read mode.
12. Status read during read mode (data output)
The memory data cannot be output only by the RE clock, after the transition from the status read mode to
the read mode by the 7Fh, when the device is set to the status read mode during the data output, in the read
mode.
In this case, 06h command, column address, page address and E0h command must be input to the read
operation.
13. Status read in Multibank program mode
When execute status read during a dummy busy period after input command 11h in multibank program,
judge only Ready/Busy.
Rev.4.00, Jun.20.2004, page 88 of 89