HN29V1G91T-30 Datasheet, PDF (86/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
erase/program/read operation, the command operation is forced to terminate and the applied page data is
not guaranteed.
8. Notes on the power supply down
Please do not turn off a power supply in erase busy operation.
It is required to take the following measures on system side for expected power down.
When the power down is recognized to have occurred during erase busy operation, device recovery mode
after the power on. The data in other blocks are protected, though the data in the applied block is invalid,
by doing this.
R/B
I/O
Busy
00h CA1 CA2 RA1 RA2 38h
t_DRC
Busy
00h CA1 CA2 RA3 RA4 38h
t_DRC
Address input
Notes: 1. Please input any address for CA1 and CA2. Input an arbitrary address to CA1 and CA2.
2. The address input is necessary for RA1 and RA2 and RA4. Input 00h respectively.
For RA3, input 04h.
3. Busy time (t_DRC) is as follows. When the data protect operation is unnecessary, end at the typ
time in normal operation. When the data protect operation is executed, the time of 100ms or
less is needed.
4. This protect operation is pause to input FF command or RES = L. In case of this pause, the
protect operation is not guaranteed.
typ
max
t_DRC
890µs
100ms
R/B
I/O
00h CA1 CA2 RA1 RA2 38h
R/B
I/O
00h CA1 CA2 RA1 RA2 38h
RES
FFh
tRSTDR
=350µs max
tRSTDR
=350µs max
350µs min
Rev.4.00, Jun.20.2004, page 86 of 89