HN29V1G91T-30 Datasheet, PDF (10/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Device Operation
Page Read
It becomes Busy state with WE rising edge after writing 00h along with four address cycles and 30h and
data transfer starts from memory array to the data register. The device output the data serially from
specified column address when inputting address by the repetitive high to low transition of the RE clock
after it is Ready state.
It is possible to shorten Busy time after the 2nd page when the data of page overlapped to 4 bank
consecutively like Page 0, Page1, Page 2, Page 3 is read out (Please see 4 page read below).
The data of Page 1 to Page 3 are transferred to the data register when writing 00h and 30h specifying
column address and Page 0.
The device output the data of Page 0 serially by clocking RE after transferring it from memory array to the
data register.
The data of Page 1, Page 2, Page 3 which are transferred to the data register can be output using Page data
out command (06h/E0h) after the data of Page 0 output.
Rev.4.00, Jun.20.2004, page 10 of 89