HN29V1G91T-30 Datasheet, PDF (51/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
AC Timing Characteristics for Operation
Parameter
Symbol Min Typ Max Unit Note
Data Transfer from Cell to Register
t_R
  120 µs
ALE to RE Delay (ID Read)
t_AR1
20  
ns
ALE to RE Delay (Read cycle)
t_AR2
30  
ns
CLE to RE Delay (Read cycle)
t_CLR
6

ns
Ready to RE Low
t_RR
20  
ns
RE Pulse Width
t_RP
20  
ns
WE High to Busy
t_WB
  100 ns
Read cycle time
t_RC
35  
ns
RE Access Time
t_REA
  20
ns
CE Access Time
t_CEA
  25
ns
RE High to Output Hi-Z
t_RHZ
10  20
ns 1
CE High to Output Hi-Z
t_CHZ
0
 20
ns 1
RE High Hold Time
t_REH
10  
ns
Output Hi-Z to RE Low
t_IR
0

ns
WE High to RE Low
t_WHR
50  
ns
Device Resetting Time
Read
t_RSTR

20
µs
Program
t_RSTP

70
µs
Erase
t_RSTE

400 µs
Erase Verify
t_RSTEV


30
µs
Device recovery t_RSTDR  
350 µs
Power on busy Time
t_PON
  200 µs
V_CC Setup time to Reset
t_VRS
100  
µs
V_CC to Ready
t_VRDY

100 µs
Reset to Busy
t_BSY
  100 ns
WP setup time to WE High
t_WWS
15 

ns
WP hold time to WE High
t_WWH
15 

ns
CE setup time to Deep standby
t_CSD
100  
ns
Note: 1. The time until it becomes Hi-Z depends on the earliest signal which CE and RE go to high.
Rev.4.00, Jun.20.2004, page 51 of 89