HN29V1G91T-30 Datasheet, PDF (31/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Program Data Input in Erase Busy (recommend pattern when error occurred) Multi Bank Mode
R/B
tBERS
I/O
R/B
60h RA × 2 60h RA × 2 D0h
1 ^{Block0 (Bank0),}
Erase Block1 (Bank1)
tBERS
80h CA × 2 RA × 2 Data 11h
80h CA × 2 RA × 2 Data
1 ^{*1 Specify a page program}
Page0 (Bank0)
*2 Specify a page program
Page1 (Bank1) ₁
tDBSY
Erase
70h
Status
2 Error only Block0
(Bank0)
tPROG
I/O
FFh
60h RA × 2 D0h
Erase
70h _Status
Reset
3 _address
4 Block2 in Bank0 erase execute
infornation
Pass
85h CA × 2 RA × 2 11h
Specify the address (same as *1, *2)
again for programming
5
85h CA × 2 RA × 2 10h
5
1
Bank0
Block0
Erase
Bank1
Block1
Erase
2
3
Block0
erase error
FFh
command
Address
reset
4
Bank0
Block2
Bank1
Block1
Erase
5
Bank0
Bank1
Block1
Block2
Program
Program
Data0
80h–CA0–RA0
–(Data0)–11h
Data1
80h–CA0–RA1
–(Data1)
Data0
60h–RA2–D0h
(erase only block2)
Data1
Data0
Data1
85h–CA0–RA2 85h–CA0–RA1
–11h
–10h
It is not necessary to reset by command FFh, when transmit the writing data in erase block and 1 page in
same bank, and execute writing during erasing 1 block data, or erasing error occurs and erasing another
block in same bank. But in this case, as shown in following figure, it is necessary to specify the address for
re-programming, after erasing another block address.
Write address specifying it by command 85h at the address for re-programming in the same bank, when
writing it as shown in following figure.
Program Data Input in Erase Busy (recommend pattern when error occurred) Single Bank Mode
R/B
I/O
R/B
I/O
60h RA × 2 D0h
tBERS
80h CA × 2 RA × 2 Data
70h
*1 Specify a page program
70h
Status
Check
Pass
85h CA × 2 RA × 2 10h
Specify the address (same as *1)
for re-programming
tPROG
Erase
Status
error
tBERS
60h RA × 2 D0h
Another address in Same Bank
(same as *1) erase execute input
70h
Program
Status
Rev.4.00, Jun.20.2004, page 31 of 89