HN29V1G91T-30 Datasheet, PDF (32/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Block Erase
Erase operation for one block which is consisted of 2 page can be executed. One block is consisted of
pageN and page(N+4)
(Ex: page0 and page4, page1 and page5).
Input page address (A14 = V_IL) in lower side, when erase block address input.
Multi Block Erase
Erase operation for one block in maximum 4 bank is executed simultaneously. Any block in a bank can be
chosen. Input page address (A14 = V_IL) in lower side, when erase block address input.
Page mode Erase Verify
Whether any one page address is erased or not is verified in this mode. Verification starts internally inside
the device after writing D2h command after 60h command and row address input. It can be verified
whether the page address is erased or not after by writing 70h command (status read command) after it
becomes ready.
Block mode Erase Verify
Whether any one block is erased or not is verified in this mode. Verification starts internally inside the
device after writing D3h command after 60h command and row address input. It can be verified whether
the block is erased or not after by writing 70h command (status read command) after it becomes ready.
Multi Bank Page mode Erase Verify
Page mode erase verify for each page in maximum 4bank is executed. It can be verified whether page
address in each bank is erased or not by writing 71h command (status read command) after it becomes
ready.
Multi Bank Block mode Erase Verify
Block mode erase verify for each block in maximum 4bank is executed. It can be verified whether the
block in each bank is erased or not by writing 71h command (status read command) after it becomes ready.
Read ID
ID code can be read out by inputting the address (00h) after writing 90h command.
Manufacturer code (07h) and Device code (01h) can be read out serially by clocking RE.
Rev.4.00, Jun.20.2004, page 32 of 89