HN29V1G91T-30 Datasheet, PDF (8/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Mode selection
The address input, command input, and data input/output operation of the device are controlled by RES,
WP, WE, CE, CLE, ALE, RE, PRE signals. The following shows the operation logic table.
Logic Table
Mode
RES*³
WP*³
CE WE CLE ALE RE
Read Mode Command Input
H
×
L
H
L
H
Address Input
H
(4clock)
×
L
L
H
H
Write Mode Command Input
H
H
L
H
L
H
Address Input
H
(4clock)
H
L
L
H
H
Data Input
H
H
L
L
L
H
Data Output
H
×
L
H
L
L
During Read (Busy)
H
×
L
H
L
L
H
During Program (Busy)
H
H
×
×
×
×
×
During Erase (Busy)
H
H
×
×
×
×
×
Write Protect
H
L
×
×
×
×
×
Stand-by
H
V_SS ± 0.2 V H
×
×
×
×
/V_CC ± 0.2 V
Deep Stand-by
V_SS ± 0.2 V V_SS ± 0.2 V ×
×
×
×
×
/V_CC ± 0.2 V
Notes: 1. H: V_iH, L: V_iL, ×: V_iH or V_iL
2. PRE must be “H” fix when using Power On Auto Read and “L” fix when not using it.
3. RES, WP, PRE must be set L: V_iLD, H: V_iHD, ×: V_iHD or V_iLD
PRE*³
×*²
×*²
×*²
×*²
×*²
×*²
×*²
×*²
×*²
×*²
V_SS ± 0.2 V
/V_CC ± 0.2 V
V_SS ± 0.2 V
/V_CC ± 0.2 V
Program/Erase Characteristics
Symbol Min
Program Time
t_PROG

Cache Program Time
t_CPROG

Dummy Busy for Cache Program
t_CBSY

Dummy Busy Time
t_DBSY
1
Number of Partial Program Cycles in a Same Page N

Block Erase Time
Page mode Erase Verify Time
Block mode Erase Verify Time
t_BERS

t_PEV

t_BEV

Typ Max Unit Notes
0.6 2.4 ms
0.6 4.8 ms
3
2400 µs

4
µs

8
cycles
0.65 20
ms

50
µs

70
µs
Rev.4.00, Jun.20.2004, page 8 of 89