HN29V1G91T-30 Datasheet, PDF (13/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Multi Bank Read
Multi Bank Read operation enables to read the data of any Page address in 4 bank. Writing 00h command
with four address cycles can be specified to maximum 4 Bank. There is no restriction on an order of a
Bank to specify.
Page address specified later becomes effective when it is specified twice in the same Bank.
The device become Ready state at rising edge of WE after writing 31h command with specifying address
and the data transfer from the memory array to the data register is started.
After it becomes Ready state, it executes specifying a bank for read and column address for starting read by
writing 06h and E0h command with four address cycles. After that the device output the data serially from
column address which is specified by clocking RE. It is possible to specify any bank for read and to read
the data which is transferred to the data register repeatedly.
R/B
t_R
(A)
column J
page N
column K
page P
column L
page Q
column M
page R
I/O ^{00h Address 00h Address 00h Address 00h Address 31h}
Bank0
Bank1 ₍₁₎ Bank2
Bank3
column J’
page N
06h Address E0h D_OUT
Bank0 ₍₂₎
D_OUT
column K’
page P
06h Address E0h D_OUT
Bank1 ₍₃₎
D_OUT (B)
R/B^(A)
I/O (B)
column L’
page Q
06h Address E0h D_OUT
Bank2 ₍₄₎
D_OUT
column M’
page R
06h Address E0h D_OUT
Bank3 ₍₅₎
D_OUT
Memory array
Data register
Bank 0
Page N
Bank 1
Page P
Memory array
Bank 0
Page N
Bank 1
Page P
Data register
column J’
(2)
column K’
(3)
Note: 1. (2) (3) (4) (5): repeatable
Bank 2
Page Q
(1)
Bank 2
Page Q
column L’
(4)
Bank 3
Page R
Bank 3
Page R
column M’
(5)
Rev.4.00, Jun.20.2004, page 13 of 89