HN29V1G91T-30 Datasheet, PDF (19/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Cache Program
Cache program operation enables to use the data register of the bank which do not program as the cache
register.
The program data for next page address is transferred to Flash memory from external data buffer by using
the cache register while programming the primary data.
Setup for program starts after writing 15h command following 80h command and program address/data
transfer.
After that the device is in the Busy state. The data register of the bank which do not program is cleared
when program operation inside the device starts and then it is ready to receive the data of next page
address.
In this case next page address must be different page address of the bank with one which programs just
before.
It is prohibited to program the data to page address in same bank consecutively using cache program.
Next page address for program should specify one in different bank.
The data of next page address can be transferred to Flash memory by writing 80h command as well as the
data transfer of the1st page address and then 15h command (program dummy command) input is required
after program address/data input. It becomes Busy state until the program operation to the 1st page address
completes and the data of data register is cleared. If the program operation to the 1st page address does not
complete, it becomes Busy state until the data of data register except for one of the bank which programs
next.
70h command is issued to find out the status in cache program operation after Ready/Busy becomes Ready.
The True Ready/Busy status (I/O5) in cache program becomes busy when CPU is active and shows that the
internal program operation is in the process. The True Ready/Busy status (I/O6) should be verified to find
out the program completion if 15h command is used for the last programming. Reset operation is required
by writing FFh when program operation completes using 15h command and moves to the other operation
except for cache program. Reset operation is not required if 10h command (program start command) is
used for the last programming.
R/B
I/O
t_CBSY
80h ^Address, 15h
Data
(1) ^{1st page}
70h Status
(2)
R/B (A)
t_CBSY
I/O (B) 80h ^Address, 15h
Data
(M-1) th page
(7)
(8)
70h Status
t_CBSY
80h ^Address, 15h
Data
2nd page
(3)
70h Status
(4)
t_{CBSY (A)}
80h ^Address, 15h
(B)
Data
3rd page
(5)
t_CBSY
t_CPROG
80h ^Address, 15h
Data
M th page
70h Status
80h
Address,
Data
150h
(M+1) th page
70h Status
Bank 0
Memory Array
Page N
Program ₍₂₎
Data Register
(1)
Bank 1
Page P
Program ⁽⁴⁾
(3)
Bank 2
Page Q
Program (6)
(5)
Bank 3
Page R
Program (8)
(7)
Rev.4.00, Jun.20.2004, page 19 of 89