HN29V1G91T-30 Datasheet, PDF (14/92 Pages) Renesas Technology Corp – 128M X 8-bit AG-AND Flash Memory

HN29V1G91T-30
Multi Bank Read Random Data output
The data can be read out setting column address freely on the way to the read operation of Page address
data in each Bank in Multi Bank Read operation. It is possible to read out the data by writing 05h and E0h
command with two column address cycles. There is no restriction to specify any column address and it is
possible to specify it including same one in the same page address many times.
R/B
t_R
(A)
column J
page N
column K
page P
column L
page Q
column M
page R
I/O ^{00h Address 00h Address 00h Address 00h Address 31h}
(1)
column J’
page N
06h Address E0h D_OUT
column J’’
D_OUT
05h Address E0h D_OUT
(2)
D_OUT (B)
R/B
(A)
(C)
column K’
I/O
page P
(B) 06h Address E0h D_OUT
column K’’
D_OUT 05h Address E0h D_OUT
(3)
D_OUT
column L’
page Q
06h Address E0h D_OUT
column L’’
D_OUT 05h Address E0h D_OUT
(4)
D_OUT (D)
R/B
(C)
column M’
I/O
page R
(D) 06h Address E0h D_OUT
D_OUT
column M’’
05h Address E0h D_OUT
(5)
D_OUT
Memory array
Bank 0
Page N
Bank 1
Page P
Bank 2
Page Q
Data register
Memory array
Bank 0
Page N
(1)
Bank 1
Bank 2
Page P
Page Q
Data register
column J’
(2) ^{column J’’}
column K’
(3) ^{column K’’}
column L’
(4) ^{column L’’}
Note: 1. (2) (3) (4) (5): repeatable
Bank 3
Page R
Bank 3
Page R
column M’
(5) ^{column M’’}
Rev.4.00, Jun.20.2004, page 14 of 89