M37281EKSP Datasheet, PDF (82/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Both HSYNC signal and VSYNC signal are negative-polarity input
HSYNC
Field
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
VSYNC and
VSYNC
control
(n–1) field
(Odd-numbered)
signal
T1
in microcom-
puter
Upper :
VSYNC signal
(n) field
(Even-numbered)
T2
Lower :
VSYNC control
signal in
micro-
computer
(n+1) field
(Odd-numbered)
T3
0.25 to 0.50[µs] at
f(XIN) =8 MHz
Odd
0
Even 0 (T2 > T1)
1
0
Odd
1 (T3 < T2)
1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A16) to “0.”
Dot line 1
Dot line 0
Dot line 0
Dot line 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CC mode · CDOSD mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSDS mode
When the display dot line selection bit is “0,”
the “ ” font is displayed at even field, the
“ ” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 8.11.19 Relation Between Field Determination Flag and Display Font
Rev.1.01 2003.07.16 page 82 of 170