M37281EKSP Datasheet, PDF (23/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
Name
Functions
After reset R W
0 Timer 1 interrupt
request bit (TM1R)
0 : No interrupt request issued _{0 R ✽}
1 : Interrupt request issued
1 ^{Timer 2 interrupt}
request bit (TM2R)
0 : No interrupt request issued _{0 R ✽}
1 : Interrupt request issued
2 ^{Timer 3 interrupt}
request bit (TM3R)
0 : No interrupt request issued 0 R ✽
1 : Interrupt request issued
3 ^{Timer 4 interrupt}
request bit (TM4R)
0 : No interrupt request issued ₀ R ✽
1 : Interrupt request issued
4 OSD interrupt request
0 : No interrupt request issued 0 R ✽
bit (OSDR)
1 : Interrupt request issued
5 VSYNC interrupt
0 : No interrupt request issued 0 R ✽
request bit (VSCR)
1 : Interrupt request issued
6 A-D conversion • INT3
0 : No interrupt request issued 0 R ✽
external interrupt request _{1 : Interrupt request issued}
bit (ADR)
7 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0 ^R—
✽ : “0” can be set by software, but “1” cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt request register 2 (IREQ2) [Address 00FD16]
B
Name
Functions
After reset _{R W}
0 INT1 external interrupt
request bit (IN1R)
0 : No interrupt request issued ₀
1 : Interrupt request issued
R✽
1 Data slicer interrupt
request bit (DSR)
2 Serial I/O interrupt
request bit (SIOR)
0 : No interrupt request issued 0
1 : Interrupt request issued
0 : No interrupt request issued ₀
1 : Interrupt request issued
R✽
R✽
3 f(XIN)/4096 • SPRITE OSD
0 : No interrupt request issued 0
interrupt request bit (CKR)
1 : Interrupt request issued
4 INT2 external interrupt request 0 : No interrupt request issued 0
bit (IN2R)
1 : Interrupt request issued
5 Multi-master I²C-BUS interrupt ^{0 : No interrupt request issued} 0
request bit (IICR)
1 : Interrupt request issued
6 Timer 5 • 6 interrupt
request bit (TM56R)
0 : No interrupt request issued ₀
1 : Interrupt request issued
R✽
R✽
R✽
R✽
7 ^{Fix this bit to “0.”}
0
RW
✽: “0” can be set by software, but “1” cannot be set.
Fig. 8.3.3 Interrupt Request Register 2
Rev.1.01 2003.07.16 page 23 of 170