M37281EKSP Datasheet, PDF (139/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Structure of Register
The figure of each register structure describes its functions, contents
at reset, and attributes as follows:
<Example>
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
11 00
Bits position
Bit attributes ^{(Note 2)}
Values immediately after reset release (Note 1)
CPU mode register (CPUM) (CM) [Address 00FB16]
B
Name
0, 1 Processor mode bits
(CM0, CM1)
Functions
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
After reset R W
0 RW
2 Stack page selection ^{0: 0 page}
bit (See note) (CM2) 1: 1 page
0 RW
3, 4 Fix these bits to “1.”
1 RW
5 Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “0.”
6, 7 Clock switch bits
(CM6, CM7)
b7 b6
0 0: f(XIN) = 8 MHz
0 1: f(XIN) = 12 MHz
1 0: f(XIN) = 16 MHz
1 1: Do not set
1 RW
0 RW
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0 ••••••••••••••••••“0” after reset release
1 ••••••••••••••••••“1” after reset release
Indeterminate•••Indeterminate after reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
R ••••••Read enabled
– ••••••Read disabled
W••••••Write
W _{••••••Write enabled}
– ••••••Write disabled
✽ ••••••“0” can be set by software, but “1”
cannot be set.
Rev.1.01 2003.07.16 page 139 of 170