M37281EKSP Datasheet, PDF (78/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.11.3 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1,
main clock) in the pre-divide circuit. The clock cycle divided in the
pre-divide circuit is defined as 1TC.
The dot size is specified by bits 6 to 3 of the block control register.
Refer to Figure 8.11.4 (the block control register i), refer to Figure
8.11.6 (the clock control register).
The block diagram of dot size control circuit is shown in Figure 8.11.14.
Notes 1: The pre-divide ratio = 3 cannot be used in the CC mode.
2: The pre-divide ratio of the layer 2 must be same as that of the layer 1
by the block control register i.
3: In the bi-scan mode, the dot size in the vertical direction is 2 times as
ompared with the normal mode. Refer to “8.11.13 Scan Mode” about
the scan mode.
OSC1
Data slicer clock
(See note)
HSYNC
Synchronous
circuit
Cycle ✕ 2
Clock cycle
= 1TC
Cycle ✕ 3
Pre-divide circuit
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 8.11.14 Block Diagram of Dot Size Control Circuit
1 dot
1TC
1TC
1/2H
1H
2TC
2H
3TC
3H
Scanning line of F1 (F2)
Scanning line of F2 (F1)
In normal scan mode
Fig. 8.11.15 Definition of Dot Sizes
Rev.1.01 2003.07.16 page 78 of 170