M37281EKSP Datasheet, PDF (65/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/2¹³ or
f(XIN)/2¹³ is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816).
Figure 8.10.12 shows the structure of the sync pulse counter and
Figure 8.10.13 shows the synchronous signal counter block diagram.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E916]
B
Name
Functions
0 Count value (HC0 to HC4)
to
4
5 Count source (HC5)
0: HSYNC signal
1: Composite sync signal
After reset ^{R W}
Indeterminate R —
0
RW
6, 7 Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0
R—
Fig. 8.10.12 Sync Pulse Counter Register
f(XIN)/2¹³
Composite
sync signal
HSYNC signal
Selection gate : connected to black
side when reset.
Reset
5-bit counter
Counter
b5
Latch (5 bits)
Sync pulse
counter register
Data bus
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
Rev.1.01 2003.07.16 page 65 of 170