M37281EKSP Datasheet, PDF (81/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.11.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.19) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.9) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field.
The field determination flag changes at a rising edge of VSYNC con-
trol signal in the microcomputer.
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 8.11.19).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I/O polarity control register (PC) [Address 021716]
B
Name
0 HSYNC input polarity
switch bit (PC0)
Functions
0 : Positive polarity input
1 : Negative polarity input
After reset R W
0
RW
1 VSYNC input polarity
switch bit (PC1)
0 : Positive polarity input
1 : Negative polarity input
0
RW
2 R, G, B output polarity
switch bit (PC2)
0 : Positive polarity output
1 : Negative polarity output
0
RW
3 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0”.
0
R—
4 OUT1 output polarity
switch bit (PC4)
0 : Positive polarity output
0
RW
1 : Negative polarity output
5 OUT2 output polarity
switch bit (PC5)
0 : Positive polarity output
0
RW
1 : Negative polarity output
6 Display dot line selection
bit (PC6) (See note)
0 : “ ” at even field
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
0
RW
7 Field determination
flag(PC7)
0 : Even field
1 : Odd field
1
R—
Note: Refer to Fig. 8.11.19.
Fig. 8.11.18 I/O Polarity Control Register
Rev.1.01 2003.07.16 page 81 of 170