M37281EKSP Datasheet, PDF (127/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
15. MULTI-MASTER I²C-BUS BUS LINE CHARACTERISTICS
Symbol
Parameter
Standard clock mode High-speed clock mode
Unit
Min.
Max.
Min.
Max.
tBUF
tHD; STA
tLOW
tR
tHD; DAT
tHIGH
Bus free time
Hold time for START condition
LOW period of SCL clock
Rising time of both SCL and SDA signals
Data hold time
HIGH period of SCL clock
4.7
1.3
µs
4.0
0.6
µs
4.7
1.3
µs
1000 20+0.1Cb 300
ns
0
0
0.9
µs
4.0
0.6
µs
tF
Falling time of both SCL and SDA signals
300 20+0.1Cb 300
ns
tSU; DAT
tSU; STA
tSU; STO
Data set-up time
Set-up time for repeated START condition
Set-up time for STOP condition
250
100
ns
4.7
0.6
µs
4.0
0.6
µs
Note: Cb = total capacitance of 1 bus line
SDA
tBUF
P
SCL
tLOW
tR
S
tHD;STA
tSU;STO
tF
Sr
P
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
S : Start condition
Sr : Restart condition
P : Stop condition
Fig.15.1 Definition Diagram of Timing on Multi-master I²C-BUS
Rev.1.01 2003.07.16 page 127 of 170