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M37281EKSP Datasheet, PDF (52/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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M37281MAHâXXXSP,M37281MFHâXXXSP,M37281MKHâXXXSP, M37281EKSP
8.8.6 Conversion Method
â Set bit 7 of the interrupt input polarity register (address 021216) to
â1â to generate an interrupt request at completion of A-D conver-
sion.
â Set the A-D conversion · INT3 interrupt request bit to â0â (even
when A-D conversion is started, the A-D conversion · INT3 inter-
rupt reguest bit is not set to â0â automatically).
â When using A-D conversion interrupt, enable interrupts by setting
A-D conversion · INT3 interrupt request bit to â1â and setting the
interrupt disable flag to â0.â
â Set the VCC connection selection bit to â1â to connect VCC to the
resistor ladder.
â Select analog input pins by the analog input selection bit of the
A-D control register.
â
Set the A-D conversion completion bit to â0.â This write operation
starts the A-D conversion. Do not read the A-D conversion register
during the A-D conversion.
â Verify the completion of the conversion by the state (â1â) of the
A-D conversion completion bit, the state (â1â) of A-D conversion ·
INT3 interrupt reguest bit, or the occurrence of an A-D conversion
interrupt.
â Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC connec-
tion selection bit to â0â between steps â and â.
8.8.7 Internal Operation
When the A-D conversion starts, the following operations are auto-
matically performed.
â The A-D conversion register is set to â0016.â
â The most significant bit of the A-D conversion register becomes
â1, â and the comparison voltage âVrefâ is input to the comparator.
At this point, Vref is compared with the analog input voltage âVIN .â
â Bit 7 is determined by the comparison results as follows.
When Vref < VIN : bit 7 holds â1â
When Vref > VIN : bit 7 becomes â0â
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum of 50 ma-
chine cycles (12.5 µs at f(XIN) = 8 MHz) after it starts, and the con-
version result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time as A-D
conversion completion, the A-D conversion · INT3 interrupt request
bit becomes â1.â The A-D conversion completion bit also becomes
â1.â
Table 8.8.1 Expression for Vref and VREF
A-D conversion register contents ânâ
(decimal notation)
0
1 to 255
Note: VREF indicates the reference voltage (= Vcc).
Vref (V)
0
VREF â (n â 0.5)
256
Contents of A-D conversion register
A-D conversion start
00 0 00 000
1st comparison start
2nd comparison start
3rd comparison start
10000 00 0
1 1000 00 0
12 100 00 0
8th comparison start
12 3 45 6 7 1
Reference voltage (Vref) [V]
0
VREF
2
â
VREF
512
VREF
2
±
VREF
4
â
VREF
512
VREF ±
2
VREF ±
4
VREF
8
â
VREF
512
VREF
2
±
VREF
4
±
VREF
8
±
.....
.......
±
VREF â
256
VREF
512
A-D conversion completion
(8th comparison completion)
12 3 456 78
Digital value corresponding to
analog input voltage.
m : Value determined by mth (m = 1 to 8) result
Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
Rev.1.01 2003.07.16 page 52 of 170
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