M37281EKSP Datasheet, PDF (144/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Address 00E016
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
00000
Data slicer control register 1(DSC1) [Address 00E016]
B
Name
Functions
0 Data slicer and timing signal
generating circuit control bit (DSC10)
1 Selection bit of data slice reference
voltage generating field (DSC11)
2 Reference clock source
selection bit (DSC12)
3 to Fix these bits to “0.”
7
0: Stopped
1: Operating
0: F2
1: F1
0: Video signal
1: HSYNC signal
After reset R W
0 RW
0 RW
0 RW
0 RW
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Address 00E116
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Data slicer control register 2 (DSC2) [Address 00E116]
B
Name
0 Caption data latch
completion flag 1
(DSC20)
1 Fix this bit to “0.”
Functions
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
clock-run-in is determined.
After reset R W
Indeterminate R —
0
RW
2 Test bit
Read-only
3 Field determination
flag(DSC23)
0: F2
1: F1
4 _{Vertical synchronous signal} 0: Method (1)
(Vsep) generating method ^{1: Method (2)}
selection bit (DSC24)
5 _{V-pulse shape}
0: Match
determination flag (DSC25) ^{1: Mismatch}
6 Fix this bit to “0.”
7 Test bit
Read-only
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Indeterminate R —
Indeterminate R —
0
RW
Indeterminate R —
0
RW
Indeterminate R —
Vsep
F2: Hsep
Vsep
Rev.1.01 2003.07.16 page 144 of 170