M37281EKSP Datasheet, PDF (75/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
The display start position in the vertical direction is determined by
counting the horizontal sync signal (HSYNC). At this time, when VSYNC
and HSYNC are positive polarity (negative polarity), it starts to count
the rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
8 machine cycles or more
VSYNC signal input
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
HSYNC
signal input
8 machine cycles
or more
0.25 to 0.50 [µs]
( at f(XIN) = 8MHz)
(Note 2)
12345
Not count
When bits 0 and 1 of the I/O polarity control register
(address 021716) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
Fig. 8.11.9 Supplement Explanation for Display Position
Rev.1.01 2003.07.16 page 75 of 170