M37281EKSP Datasheet, PDF (17/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
s SFR2 area (addresses 20016 to 21F16)
<Bit allocation>
:
: N a m e
Function bit
: No function bit
0 : ^{Fix to this bit to “0”}
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
<State immediately after reset>
0 ^{: “0” immediately after reset}
1 : “1” immediately after reset
? : Indeterminate immediately
after reset
Address Register
Bit allocation
b7
State immediately after reset
b0 b7
b0
20016 PWM0 register (PWM0)
?
20116 PWM1 register (PWM1)
?
20216 PWM2 register (PWM2)
?
20316 PWM3 register (PWM3)
?
20416 PWM4 register (PWM4)
?
20516 PWM5 register (PWM5)
?
20516 PWM6 register (PWM6)
?
20716 PWM7 register (PWM7)
?
20816
?
20916
?
20A16 PWM mode register 1 (PN)
20B16 PWM mode register 2 (PW)
PN4 PN3
PN0
0 PW6 PW5 PW4 PW3 PW2 PW1 PW0
0016
0016
20C16 ROM correction address 1 (high-order)
0016
20D16 ROM correction address 1 (low-order)
0016
20E16 ROM correction address 2 (high-order)
0016
20F16 ROM correction address 2 (low-order)
21016
ROM correction enable register (RCR)
AD/INT3
SEL
21116 Test register
RE5
R0E3 R0E2 RRCER11 RCR0
0016
21216 Interrupt input polarity register (IP)
21316 Serial I/O mode register (SM)
21416 Serial I/O register (SIO)
21516 OSD control register 2(OC2)
AADD/I/NINT3T3_PINOTL3
SSEELL 3
RE5
POL2 P_RO_EL₃1
RE2
RE1
ASDEL/INT3_SPLI3N_MOT_{6 RSME55 SM4 RSME33 RSME22 RSME11 SM0}
PO
L
OC27 OC26 OC25 OC24 OC23 OC12 OC21 OC20
21616 Clock control register (CS)
21716 I/O polarity control register (PC)
21816 Raster color register (RC)
21916 OSD control register 3(OC3)
0 0 ^AD/INT3
SEL
0 0 ^{CRSE2 CRSE1 CS0}
AS_PDE_CL/IN7T3_PI3N_CT_{6 RPCE5 PC4 RE3 RPCE2 RPCE1 PC0}
A_RDE_CL/IN7T3_{RPLI3NCOT6 RCE55 RC4 RREC3 RREC2 RREC1 RC0}
OC37 OPCO36 OC35 OC34 ORCE33 ORCE232 ORCE131 OC30
L
21A16 Timer 5 (TM5)
0016
0016
0016
0016
0016
?
0016
0016
8016
0016
0016
FF16
21B16 Timer 6 (TM6)
0716
21C16 Top border control register 1 (TB1)
TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10
?
21D16 _{Bottom border control register 1 (BB1)} ^BB17 BB16 ^{BB15 BB14} BB13 BB12 BB11 ^BB10
?
21E16 _{Top border control register 2 (TB2)}
TB21 TB20
?
21F16 Bottom border control register 2 (BB2)
BB21 BB20
?
Fig. 8.2.6 Memory Map of Special Function Register 2 (SFR2) (1)
Rev.1.01 2003.07.16 page 17 of 170