M37281EKSP Datasheet, PDF (110/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Bottom Border Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Bottom border control register 1 (BB1) [Address 021D16]
B
Name
0 _{Control bits of}
to _{bottom border}
7 _{(BB10 to BB17)}
Functions
After reset R W
Bottom border position (low-order 8 bits) Indeterminate R W
TH✕
(setting value of low-order 2 bits of BB2 ✕16²
+ setting value of high-order 4 bits of BB1 ✕16¹
+ setting value of low-order 4 bits of BB1 ✕16⁰)
Notes 1: Set values fit for the following condition:
(TB1 + TB2 ✕ 16²) < (BB1 + BB2 ✕ 16²).
2: TH is cycle of HSYNC.
3: BB2 is bottom border control reigster 2.
Fig. 8.11.48 Bottom Border Control Register 1
Bottom Border Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Bottom border control register 2 (BB2) [Address 021F16]
B
Name
0, 1 _{Control bits of}
bottom border
(BB20, BB21)
Functions
After reset R W
Bottom border position (high-order 2 bits)Indeterminate _{R W}
TH ✕
(setting value of low-order 2 bits of BB2 ✕16²
+ setting value of high-order 4 bits of BB1 ✕16¹
+ setting value of low-order 4 bits of BB1 ✕16⁰)
2
to
7
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
Indeterminate
R—
Notes 1: Set values fit for the following condition:
(TB1 + TB2 ✕ 16²) < (BB1 + BB2 ✕ 16²).
2: TH is cycle of HSYNC.
3: BB1 is bottom border control reigster 1.
Fig. 8.11.49 Bottom Border Control Register 2
Rev.1.01 2003.07.16 page 110 of 170