M37281EKSP Datasheet, PDF (30/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as ports P1 and P7.
Bit 2 of the serial I/O mode register (address 021316) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the
pin for servial I/O, set the bit corresponding to SCLK pin of thr port
P4 direction register (address 00C916) and the bit corresponding
to SIN pin of the port P1 direction register (address 00C316) to “0”.
More over, set the bit corresponding to SOUT of rhe port P4 direction
register (address 00C916) to “1” And, to use SOUT pin for serial I/O,
set the corresponding bits of the port P4 direction register (address
00C916) to “1.”
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
XCIN
XIN
SCLK
SOUT
SIN
1/2
1/2
1/2
CM7
Synchronous
circuit
SM2
Data bus
Frequency divider
1/2 1/4 1/8 1/16
SM1
SM0
Selection gate: Connect to
black side at
reset.
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O counter (8)
SM5 : LSB
MSB
(Note)
Serial I/O shift register (8)
8 ^{(Address 021416)}
Serial I/O
interrupt request
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev.1.01 2003.07.16 page 30 of 170