M37281EKSP Datasheet, PDF (152/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Address 00FA16
I²C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I²C clock control register (S2) [Address 00FA16]
B
Name
Functions
After reset R W
0 SCL frequency control bits
to (CCR0 to CCR4)
4
Register
value
b4 to b0
Standard
clock mode
High speed
clock mode
0
00 to 02 Setup disabled _{Setup disabled}
03 Setup disabled
333
04 Setup disabled
250
05
100
400 (See note)
06
83.3
166
500/CCR value 1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at f = 4 MHz, unit : kHz)
5 SCL mode
0: Standard clock mode
0
specification bit
1: High-speed clock mode
(FAST MODE)
RW
RW
6 ACK bit
(ACK BIT)
0: ACK is returned.
1: ACK is not returned.
0
RW
7 ACK clock bit
(ACK)
0: No ACK clock
1: ACK clock
0
RW
Note: At 400 kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Address 00FB16
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 CPU mode register (CM) [Address 00FB16]
B
Name
0, 1 Processor mode bits
(CM0, CM1)
Functions
After reset R W
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
0 RW
2 Stack page selection ^{0: 0 page}
bit (CM2) (See note) 1: 1 page
1 RW
3, 4 Fix these bits to “1.”
1 RW
5 ^{XCOUT drivability}
selection bit (CM5)
0: LOW drive
1: HIGH drive
6 ^{Main Clock (XIN–XOUT)} 0: Oscillating
stop bit
1: Stopped
(CM6)
7 Internal system clock
selection bit
(CM7)
0: XIN–XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
1 RW
0 RW
0 RW
Note: This bit is set to “1” after the reset release.
Rev.1.01 2003.07.16 page 152 of 170