M37281EKSP Datasheet, PDF (33/172 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
8.6 MULTI-MASTER I²C-BUS INTERFACE
The multi-master I²C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I²C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I²C-BUS in-
terface and Table 8.6.1 shows multi-master I²C-BUS interface func-
tions.
This multi-master I²C-BUS interface consists of the I²C address reg-
ister, the I²C data shift register, the I²C clock control register, the I²C
control register, the I²C status register and other control circuits.
Table 8.6.1 Multi-master I²C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
Function
In conformity with Philips I²C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I²C control register at address 00F916) for connections between
the I²C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
Serial
data
(SDA)
Noise
elimination
circuit
b7 ^{I2C address register (S0D)} b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator
Data
control
b7
circuit
b0
I²C data shift register
S0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
b0
AL AAS AD0 LRB
MST TRX BB PIN
AL
circuit
BB
circuit
Internal data bus
I ²C status
register (S1)
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
b0
ACK
ACK FAST
BIT ^{MODE CCR4 CCR3 CCR2 CCR1 CCR0}
b7
BSEL1 BSEL0 ^10BIT
SAD
ALS
b0
ESO BC2 BC1 BC0
I²C clock control register (S2)
Clock division
I²C control register (S1D)
System clock (φ)
Bit counter
Fig. 8.6.1 Block Diagram of Multi-master I²C-BUS Interface
Rev.1.01 2003.07.16 page 33 of 170